This document relates generally to semiconductor devices and, more specifically, to methods of forming insulated gate devices and structures.
Insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs), have been used in many power switching applications, such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions and allows for majority carrier conduction between these regions.
There is a class of MOSFET devices in which the gate electrode is formed in a trench extending downward from a major surface of a semiconductor material, such as silicon. Current flow in this class of devices is primarily in a vertical direction through the device, and, as a result, device cells can be more densely packed. All else being equal, the more densely packed device cells can increase the current carrying capability and reduce on-resistance of the device.
Medium and high voltage Trench MOSFET devices used in high frequency switch mode power supply (SMPS) applications should exhibit low small-signal output capacitance (COSS) and low on-resistance (Rdson) to meet desired switching efficiency. Also, the low Rdson should be balanced with maintaining desired breakdown voltage (BVDSS) and achieving desired ruggedness, such as good unclamped inductive switching (UIS). In the past, achieving low COSS was difficult in medium voltage MOSFET devices (for example, about 40 volts to about 150 volts) because BVDSS is proportional to trench depth and COSS is also proportional to trench depth (i.e., increases with trench depth). Various techniques have been used in an attempt to lower COSS. In one technique, a thick shield electrode liner oxide and/or thick bottom oxide has been used; however, this technique resulted in higher Rdson and exhibited process yield issues. In another technique, a high resistive drift region was used; however, this technique also resulted in higher Rdson. In a further technique, a high energy ion implant was used to place dopant very deep into the drift region and spaced apart from the body region; however this technique required very expensive ion implantation equipment, suffered from process repeatability issues, and suffered from process yield issues.
Accordingly, it is desirable to have a method and structure that reduces small signal output capacitance, reduces on-resistance, improves switching characteristics, reasonably maintains BVDSS performance, reduces hot-carrier induced BVDSS walk-in/out, and improves device ruggedness. Also, it is desirable that the method and structure be compatible with existing process flows, avoid having to use expensive process equipment, and have improved process repeatability and yields.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices, a person of ordinary skill in the art understands that P-channel devices and complementary devices are also possible in accordance with the present description. For clarity of the drawings, doped regions of device structures can be illustrated as having generally straight-line edges and precise angular corners; however, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions are generally not straight lines and the corners are not precise angles.
Furthermore, the term “major surface” when used in conjunction with a semiconductor region or substrate means the surface of the semiconductor region or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.
In addition, structures of the present description can embody either a cellular-base design (in which the body regions are a plurality of distinct and separate cellular or stripe regions) or a single-base design (in which the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with connected appendages). However, one embodiment of the present description will be described as a cellular base design throughout the description for ease of understanding. It should be understood that the present disclosure encompasses both a cellular-base design and a single-base design.